Part Number Description Status Features Rating Cross Refeence VCCA (Min) (V) VCCA (Max) (V) VCCB (Min) (V) Frequency (Max) (kHz) VCCB (Max) (V) Supply restrictions Pin/Package
AT9511 2019Q4 Buffer, Enable Pin Industry PCA9511 2.7 5.5 2.7 400 5.5 VCC Single Supply MSOP8 SOP8


     The AT9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the AT9511A provides bidirectional buffering, keeping the backplane and card capacitances isolated.

   The AT9511A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The AT9511A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW).

      During insertion, the AT9511A SDA and SCL lines are precharged to 1V to minimize the current required to charge the parasitic capacitance of the chip.


    Bidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems

    Compatible with I2C-bus Standard-mode, I2C-bus Fast-mode, and SMBus standards

    Built-in DV/Dt rise time accelerators on all SDA and SCL lines (0.6 V threshold) requires the bus pull-up voltage and supply voltage (VCC) to be the same

    Active HIGH ENABLE input

    Active HIGH READY open-drain output

    High-impedance SDA and SCL pins for VCC = 0 V

    1 V precharge on all SDA and SCL lines

    Supporting clock stretching and multiple master arbitration/synchronization

    Operating power supply voltage range: 2.7 V to 5.5 V

    0 Hz to 400 kHz clock frequency

    ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

    Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

    Packages offered: SO8, TSSOP8 (MSOP8)


    cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system

Application design-in information


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