The AT9545A/45B/45C is a quad bidirectional translating switch controlled via the
I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of the four interrupt inputs.
An active LOW reset input allows the AT9545A/45B/45C to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected as does the internal power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which is passed by the PCA9545A/45B/45C. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The AT9545A, AT9545B and AT9545C are identical except for the fixed portion of the slave address.

1-of-4 bidirectional translating switches
I2C-bus interface logic; compatible with SMBus standards
4 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I2C-bus
Alternate address versions A, B and C allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts
Channel selection via I2C-bus, in any combination
Power-up with all switch channels deselected
Low Ron switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant Inputs
0 Hz to 400 kHz clock 

Typical Application